1. Field of the Invention
The present invention relates to memory devices including phase change-based memory materials, including chalcogenide-based materials and other programmable resistance materials, and methods for manufacturing such devices.
2. Description of Related Art
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher electrical resistivity. These materials are the basis for integrated circuit phase change memory devices, and other memory technologies.
The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in the amorphous state.
The magnitude of the current needed for reset can be reduced by reducing the size of the phase change material element in the cell and/or the contact area between electrodes and the phase change material, such that higher current densities are achieved with small absolute current values through the phase change material element.
Research has progressed to provide memory devices that operate with low reset current by adjusting a doping concentration in phase change material, and by providing structures with very small dimensions. One problem with very small dimension phase change devices involves endurance. Specifically, the resistance of memory cells made using phase change materials in a set state can drift as the composition of the phase change material slowly changes with time over the life of the device. Co-pending U.S. patent application entitled DIELECTRIC MESH ISOLATED PHASE CHANGE STRUCTURE FOR PHASE CHANGE MEMORY, U.S. application Ser. No. 12/286,874 (now U.S. Patent Publication No. 2010-0084624), filed 2 Oct. 2008 (MXIC 1849-1), addresses some of the issues discussed above related to changes in composition of the phase change memory during the first few cycles operation. U.S. application Ser. No. 12/286,874 is incorporated by reference as if fully set forth herein. Also, composite doping has been described as a technology for stabilizing phase change materials, in co-pending U.S. patent application Ser. No. 12/729,837, entitled PHASE CHANGE MEMORY HAVING ONE OR MORE NON-CONSTANT DOPING PROFILES, filed 23 Mar. 2010 (MXIC 1911-2), which is incorporated by reference as if fully set forth herein.
This drift can cause problems with reliability and increase in complexity of control circuitry needed to operate the devices. For example, if the resistance drifts on set or/and reset state cells, phase change speed changes, the dynamic resistance of the cells may change, different retention behaviors (resistance stability) are encountered, and so on. One result of these problems is that the sensing circuitry required on the devices must handle wider ranges of resistance for each of the memory states, which typically results in lower speed operation. Also, the set and reset processes must account for varying bulk conditions of the memory cells even within a single memory state, which typically results in uneven set and reset speeds across the array.
Co-inventor Ming-Hsiu Lee has described in co-pending U.S. patent application Ser. No. 12/484,955, filed 15 Jun. 2010 (MXIC 1879-1), a memory device having a phase change material element with a modified stoichiometry in the active region, which does not exhibit the drift in set state resistance of prior art memory devices. U.S. patent application Ser. No. 12/484,955 is incorporated by reference as if fully set forth herein. Also, a method for manufacturing the memory device is described in U.S. patent application Ser. No. 12/484,955 that includes first manufacturing an integrated circuit including an array of phase change memory cells with bodies of phase change material having a bulk stoichiometry; and then applying forming current to the phase change memory cells in the array to change the bulk stoichiometry in active regions of the bodies of phase change material to the modified stoichiometry, the modified stoichiometry being different than the bulk stoichiometry, and without disturbing the bulk stoichiometry outside the active regions. The bulk stoichiometry is characterized by stability under the thermodynamic conditions outside the active region, while the modified stoichiometry is characterized by stability under the thermodynamic conditions inside the active region. By establishing the bulk and modified stoichiometry in the memory element, the set state resistance of the memory cell is stabilized over the lifetime of the cell, which can extend to millions of set/reset cycles and more. The body of phase change material used as a memory element adopts a stabilized microstructure in which the stoichiometry is non-uniform, having a different atomic concentration profile in the active region than is found outside the active region of the body of phase change material. The transition in stoichiometry of the body of phase change material is not abrupt, but rather occurs across a transitional zone along the boundaries of the active region. The transitional zone characteristics will vary according to the structure of the memory cell, the type of forming current applied, and other factors. The term “stoichiometry” as used here refers to the quantitative relationship in atomic concentration between two or more substances in the phase change material in a volume measurable, for example, using energy dispersive x-ray spectroscopy (EDX), or equivalent techniques.
In addition to the issues discussed above, the write bandwidth of phase change memory is one characteristic that can limit the types of memory mission functions for which it can be used in an integrated circuit. The write bandwidth for this kind of memory is limited by the set operation speed rather than reset. This is because the set time is 5 to 10 times greater than that of the reset. However, the set current amplitude is 50%˜70% of the reset.
In general, system-on-chip (SOC) technology is the integration of multiple subsystems of an electronic system within a single integrated circuit, and may contain digital, analog, mixed-signal, and radio-frequency functions. The various types of subsystems that may be integrated within the integrated circuit include microprocessor and microcontroller cores, digital signal processors (DSPs), configurable logic units, memory blocks, timing sources, external interfaces, and power management circuits, among others. An SOC consists of both the hardware described above, as well as the software that controls the subsystems. The term “system-on-a-chip” may be used to describe complex application specific integrated circuits (ASIC), where many functions previously achieved by combining multiple integrated circuits on a board are now provided by one single integrated circuit. This level of integration greatly reduces the size and power consumption of the system, while generally also reducing manufacturing costs.
In order to fulfill the memory performance requirements for the various functions of the SOC, different types of memory circuits serving different purposes of mission functions are typically embedded at various locations in the integrated circuit for memory applications such as random access memory (RAM), flash memory, and read only memory (ROM). However, integration of different types of memory devices for the various memory applications in an SOC can be difficult and result in highly complex designs and manufacturing processes.
Accordingly, it is desirable to provide a memory cell structure having more stable operation over the life of the device, and to provide for higher speed operations.
It is also desirable to provide memory on a single integrated circuit addressing different memory performance requirements such as those demanded of the various functions of SOCs, while also addressing the issue of design integration. It is also desirable to provide methods for manufacturing such devices.
It is also desirable to provide a memory technology that can be adapted for use in many mission functions.